HPE J9535A 20-port Gig-T PoE+ / 4-port SFP v2 zl switch module
- HP E5400/E8200 seri…
- 20-port 10/100/1000…
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HPE Refurbished
A 12-core Xeon processor upgrade running at 2.70 GHz with 30 MB L3 cache for compatible servers
This refurbished HPE 715224-B21 upgrades compatible servers with a 12-core Intel Xeon E5-2697 v2 running at 2.70 GHz. It targets administrators refreshing older E5-2600 v2 platforms for virtualisation or database workloads. The 22 nm processor delivers 30 MB of L3 cache and supports 64-bit processing.
The processor fits the Sock socket and communicates over an 8 GT/s QuickPath Interconnect. Maximum turbo frequency reaches 3.50 GHz when thermal headroom allows. Systems must provide adequate cooling and power delivery for the 12-core design. Buyers needing a different socket or higher interconnect bandwidth cannot use this module.
As a refurbished processor upgrade, the unit arrives without original retail packaging and may show minor cosmetic wear from prior deployment. The bare die and land-grid-array contacts require careful electrostatic-safe handling during installation. Technicians should verify socket compatibility and thermal-paste condition before seating the chip. Servers lacking the correct Sock socket or BIOS support for the E5-2600 v2 series cannot accept this upgrade.
Measured against everything we stock in Switch Modules, Transceivers & Add-Ons, at today’s prices. Recalculated every night.
| Product | |
|---|---|
| Brand name | HPE |
| Power | |
| Plug type | Processor Upgrade |
| Size & build | |
| Shipping weight | 1.36 kg |
| Package size | 380 × 195 × 190 mm |
The 715224-B21 is a single 12-core Xeon E5-2697 v2 running at 2.70 GHz with 30 MB L3 cache, designed as a direct processor upgrade for compatible HPE servers.
The 2.70 GHz base frequency across 12 cores provides consistent multi-threaded throughput, while the 3.50 GHz overclocking speed allows higher single-thread performance when thermal headroom exists.
The 8 GT/s QuickPath Interconnect links the processor to the chipset and other CPUs, capping inter-socket bandwidth at that rate and limiting maximum memory bandwidth to what the socket's memory controllers can sustain.
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