Crucial CT2K8G3S160BM 16GB (2 x 8GB) DDR3 1600 SO-DIMM memory upgrade
- 16 GB (2 × 8 GB)
- DDR3 1600
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Adds 192 GB of DDR5 ECC registered memory in six 32 GB modules running at 4800 MT/s CL40 for compatible Supermicro servers
This 192GB kit contains six 32GB DDR5 4800 registered DIMMs with ECC and a CAS latency of 40. The modules run at 1.1V and use a 1Rx4 organisation on a 288-pin form factor. They are validated for the SuperMicro SYS-211E-FRN2T, SYS-211E-FRDN2T, X13SEM-F and X13SEM-TF platforms.
Administrators expanding memory in the listed SuperMicro SuperServer models will find the correct density, speed and registration here. Builders needing unbuffered DIMMs, non-ECC modules or a different pin count should look elsewhere because this kit is specifically registered ECC RDIMM.
The single specification that decides fit is the registered ECC RDIMM design combined with a 1Rx4 rank structure. Only motherboards that accept registered ECC DDR5 at 4800 MT/s with this rank configuration can use the kit.
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| Product | |
|---|---|
| Brand name | NEMIX RAM |
| Product line | SuperMicro Server/Workstation Compatible Series Memory |
| Model name | SuperMicro DDR5 4800 MHz ECC RDIMM Registered Server Memory |
| Part number | MR38400-314K6 |
| Total capacity | 192 GB (6 × 32 GB) |
| Product type | 288-Pin DDR5 RDIMM |
| Performance | |
| Rated speed | DDR5 4800 (PC5 38400) |
| Processor | |
| Chipset | Major OEM Samsung, Micron, Hynix |
| Memory | |
| CAS latency | CL40 |
| ECC support | Yes |
| Buffer type | Registered |
| Heat spreader | No |
| Memory rank | 1Rx4 |
| Power | |
| Rated voltage | 1.1 V |
| Compatibility | |
| Compatible systems | Supermicro |
| In the box | |
| Included items | 192 GB (6 × 32 GB) DDR5 4800 MHz PC5-38400 1Rx4 1.1 V CL40 288-PIN ECC RDIMM Registered Server Memory KIT |
Yes — the kit is specified at DDR5 4800 MT/s with CAS latency 40, so the peak transfer rate is PC5-38400.
Six 288-pin DDR5 RDIMM slots; the kit contains six 32 GB modules.
Follow the motherboard manual — populate the first slot of each memory channel before adding a second module to any channel.
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