Crucial CT2K8G3S160BM 16GB (2 x 8GB) DDR3 1600 SO-DIMM memory upgrade
- 16 GB (2 × 8 GB)
- DDR3 1600
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A 32 GB DDR5 4800 ECC registered DIMM kit for compatible SuperMicro servers
This 32 GB kit contains two 16 GB DDR5 4800 registered ECC modules built for Supermicro IoT SuperServer systems. It targets administrators who need validated, error-correcting memory for always-on workloads.
The DDR5 4800 interface runs at 1.1 V with CL40 latency and a single 1Rx8 rank per module. Registered buffering adds one clock cycle of command delay, which caps maximum throughput on boards that cannot drive higher speeds.
Bare green PCBs without heat spreaders keep the modules low-profile for dense 288-pin slots. The 1.1 V operation reduces thermal load, so passive airflow in a 1U chassis is usually sufficient for stable daily operation.
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| Product | |
|---|---|
| Brand name | NEMIX RAM |
| Product line | SuperMicro Server/Workstation Compatible Series Memory |
| Model name | SuperMicro DDR5 4800 MHz ECC RDIMM Registered Server Memory |
| Part number | MR38400-618K2 |
| Total capacity | 32 GB (2 × 16 GB) |
| Product type | 288-Pin DDR5 RDIMM |
| Performance | |
| Rated speed | DDR5 4800 (PC5 38400) |
| Processor | |
| Chipset | Major OEM Samsung, Micron, Hynix |
| Memory | |
| CAS latency | CL40 |
| ECC support | Yes |
| Buffer type | Registered |
| Heat spreader | No |
| Memory rank | 1Rx8 |
| Power | |
| Rated voltage | 1.1 V |
| Compatibility | |
| Compatible systems | Supermicro |
| In the box | |
| Included items | 32 GB (2 × 16 GB) DDR5 4800 MHz PC5-38400 1Rx8 1.1 V CL40 288-PIN ECC RDIMM Registered Server Memory KIT |
This kit provides 32GB as two 16GB modules, enabling dual-channel operation on supported Supermicro platforms for maximum bandwidth.
The DDR5 4800 modules run at 4800 MT/s (PC5-38400) with CL40 latency, providing the rated throughput when installed in compatible Supermicro systems.
These 288-pin DDR5 ECC Registered DIMMs require a motherboard with RDIMM support; the 1Rx8 organisation allows dense population within the platform's memory-channel limits.
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