Crucial CT2K8G3S160BM 16GB (2 x 8GB) DDR3 1600 SO-DIMM memory upgrade
- 16 GB (2 × 8 GB)
- DDR3 1600
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A 128GB DDR4-2666 ECC registered RDIMM with CL19 latency and 1.2V operation for HP Apollo PC40 and SX40 servers
This 128GB DDR4 2666 registered ECC module is built for HP Apollo PC40 and SX40 servers. It delivers 128GB of error-correcting memory in a single 288-pin DIMM running at 1.2V. The part meets JEDEC and RoHS standards for warranty-safe upgrades. It targets administrators extending the life of compatible server platforms.
This memory fits servers and workstations that require registered ECC DDR4 RDIMMs. It will not work in standard desktop computers or consumer motherboards. It also cannot be mixed with unbuffered or load-reduced ECC modules. Buyers needing non-ECC or unbuffered memory should look elsewhere.
The module uses an 8Rx4 rank configuration that the memory controller must support. CL19 latency at 2666 MT/s is fixed, with backward compatibility to 2133 and 2400 MT/s. Verify the platform accepts 8Rx4 registered DIMMs before purchase. No other specification overrides this requirement.
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| Product | |
|---|---|
| Brand name | OWC |
| Part number | 2R6D48R4128G |
| Total capacity | 128 GB |
| Product type | 288-Pin DDR4 ECC RDIMM |
| Performance | |
| Rated speed | DDR4 2666 (PC4 21300) |
| Memory | |
| CAS latency | 19 |
| ECC support | Yes |
| Buffer type | Registered |
| Memory rank | 8Rx4 |
| Heat spreader | No |
| Power | |
| Rated voltage | 1.2 V |
| Compatibility | |
| Compatible systems | HP Apollo PC40 HP Apollo SX40 |
Power down the server, open the chassis, and seat the module firmly in the correct DDR4 slot until the retention clips click. The step often missed is confirming the system requires registered ECC memory and that no unbuffered or load-reduced DIMMs are present, as mixing types will prevent boot.
The module has no heat spreader and no moving parts, so no routine maintenance is required. Replacement is only necessary if a memory error occurs or if a capacity upgrade is desired. The JEDEC-standard 1.2V design ensures long-term stability under normal server operating conditions.
The primary limit is the CL19 latency at 2666 MT/s, which fixes the minimum access delay. Under sustained load the registered buffer adds one cycle, so throughput is bounded by the 21300 MB/s peak bandwidth and the 8Rx4 organisation's rank density.
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