OWC 128GB DDR4 2933 CL21 8Rx4 288-pin 1.2V ECC LRDIMM 2L9D48R4128G memory upgrade
- 128 GB
- DDR4 2933
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A 256 GB DDR4 2933 ECC LRDIMM kit for Dell PowerEdge XR4510c and XR4520c servers
Capacity 256GB (2 x 128GB)
This 256 GB kit delivers 2 x 128 GB DDR4 2933 LRDIMM modules built for the Dell PowerEdge XR4510c and XR4520c. The ECC load-reduced design targets servers and workstations that need maximum density per slot. It will not work in standard desktops or alongside unbuffered or registered ECC memory.
Each module runs at 1.2 V with a CL21 latency profile at 2933 MT/s. The load-reduced architecture lowers electrical load on the memory bus, helping thermal headroom in dense chassis. No heat spreaders are fitted, so airflow in the server handles cooling.
The kit meets JEDEC standards and is RoHS compliant for a warranty-safe upgrade. Backward compatibility covers 2133, 2400 and 2666 MT/s speeds. OWC provides a limited lifetime warranty with free technical support and an advanced replacement programme.
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| Product | |
|---|---|
| Brand name | OWC |
| Part number | 2L9D44R4256P |
| Total capacity | 256 GB (2 × 128 GB) |
| Product type | 288-Pin DDR4 ECC LRDIMM |
| Performance | |
| Rated speed | DDR4 2933 (PC4 23400) |
| Memory | |
| CAS latency | CL21 |
| ECC support | Yes |
| Buffer type | Load Reduced |
| Memory rank | 4Rx4 |
| Heat spreader | No |
| Power | |
| Rated voltage | 1.2 V |
| Compatibility | |
| Compatible systems | Dell PowerEdge XR4510c Dell PowerEdge XR4520c |
Other versions of this model
Power down the server, open the chassis, align the notch on each 128 GB module with the slot key, and press firmly until the retention clips lock. The step often missed is populating the correct CPU-channel slots in the order shown in the system service manual; wrong order prevents POST.
No scheduled maintenance is required. If a correctable ECC error count rises above the platform threshold, the faulty 128 GB module should be replaced; otherwise the kit runs for the server's lifetime without service.
The DDR4 2933 MT/s data rate and CL21 latency set the bandwidth ceiling; under continuous heavy workloads the memory controller hits that throughput limit before thermal or voltage constraints become a factor.
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